Synopsys's new AI workflows improve chip design efficiency but validation remains a bottleneck

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Synopsys, in collaboration with Microsoft and AMD, is advancing agentic AI for autonomous EDA workflows, demonstrating 25-40% reductions in debug cycle time and improved quality of results, saving weeks of engineering effort. However, AI is effective in optimizing Power, Performance, and Area (PPA) in chip design, but validation remains a significant bottleneck, requiring human intelligence to define test specifications and ensure full coverage, as AI struggles with the vast search space.